1. Field of Invention
The present invention relates to an input-buffering device. More particularly, the present invention relates to the design of an adjustable voltage divider capable of generating a bias signal for controlling the first stage input buffering device of a NOR gate so that reversal of output signal difference at different times caused by trigger point shift is prevented.
2. Description of Related Art
Most conventional input buffering devices use a simple NOR gate structure to serve as a first stage input for transforming a transistor-transistor logic (TTL) signal into a CMOS standard sign. FIG. 1 is a circuit diagram of a conventional input-buffering device. As shown in FIG. 1, the circuit includes two PMOS transistors 10 and 12, two NMOS transistors 14 and 16 and five inverters 18, 20, 22, 24 and 26.
The source terminal of the PMOS transistor 10 is connected to a high voltage Vdd and the gate terminal is connected to a first input signal CECTL (Chip Enable Control). In addition, the source terminal of the PMOS transistor 12 is connected to the drain terminal of the PMOS transistor 10 and the gate terminal is connected to a second input signal AX. The drain terminal of the NMOS transistor 14 is connected to the drain terminal of the PMOS transistor 12. The gate terminal of the NMOS transistor 14 is connected to the second input signal AX while the source terminal is connected to a low voltage Vss. The drain terminal of the NMOS transistor 16 is connected to the drain terminal of the PMOS transistor 12. The gate terminal of the NMOS transistor 16 is connected to the first input signal CECTL while the source terminal of the NMOS transistor 16 is connected to the low voltage Vss.
The input terminal of the inverter 18 is connected to the drain terminal of the PMOS transistor 12. The input terminal of the inverter 20 is connected to the output terminal of the inverter 18, and the output terminal of the inverter 20 is connected to the drain terminal of the PMOS transistor 12. The input terminal of the inverter 22 is connected to the output terminal of the inverter 18, and the output terminal of the inverter 22 is connected to a first output signal X.sub.B. The input terminal of the inverter 24 is connected to the output terminal of the inverter 18. The input terminal of the inverter 26 is connected to the output terminal of the inverter 24, and the output terminal of the inverter 26 is connected to a second output signal X.
The trigger point of the input buffering device shown in FIG. 1 is largely determined by the dimensions of the serially connected PMOS pull-up devices (that is, PMOS transistors 10 and 12) and the parallel-connected NMOS pull-down devices (that is, NMOS transistors 14 and 16). However, different ranges of source voltage Vcc (such as 4.5-5.5V, 2.7-3.6V and 1.8-2.2V) are often required due to market forces. If related products are used with a conventional input buffering device and identical signal magnitudes are input, a trigger point shift may occur due to a different in source voltage. Hence, high-to-low or low-to-high transmission of input TTL signal may be affected, leading to reversal of output signal difference at different times produced by the NOR gate output terminal. Hence, a fast and a slow transmission will result. Such a fluctuation in transmission speed under different range of source voltage often produces different reverse speed signal that may affect access time of high-speed product (such as synchronous SRAM).